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Intel launches integrated photonics research center

SANTA CLARA, Calif .– (COMMERCIAL THREAD) –What’s new: Intel Labs recently opened the Intel® Research Center for Integrated Photonics for Data Center Interconnects. The centre’s mission is to accelerate optical input / output (I / O) technological innovation in performance scaling and integration with a focus on photonic technology and devices, CMOS circuits and link architecture, as well as package integration and fiber coupling.

“At Intel Labs, we believe that no single organization can turn all the required innovations into research reality. By collaborating with some of the greatest scientific minds in the United States, Intel is opening the doors to the advancement of integrated photonics for the next generation of computer interconnects. We look forward to working closely with these researchers to explore how we can overcome impending performance hurdles. ”

–James Jaussi, Senior Principal Engineer and Director of the PHY Research Lab in Intel Labs

Why this is important: The ever-increasing movement of data from one server to another is straining the capabilities of today’s network infrastructure. Industry is rapidly approaching the practical limits of electrical I / O performance. As demand continues to increase, the scaling of power I / O power performance is not keeping pace and will soon limit the power available for compute operations. This performance barrier can be overcome by integrating compute silicon and optical I / O, a key focus of the research center.

Intel recently demonstrated advancements in critical technology building blocks for integrated photonics. Light generation, amplification, sensing, modulation, CMOS interface circuitry, and package integration are critical to achieving the performance required to replace electricity as the primary broadband non-package interface busy.

Additionally, optical I / O has the potential to significantly outperform electrical performance in key performance measures of range, bandwidth density, power consumption, and latency. Further innovations are needed on several fronts to extend optical performance while reducing power and costs.

About the Research Center: The Intel Research Center for Integrated Photonics for Data Center Interconnects brings together world-renowned universities and researchers to accelerate optical I / O technological innovation in performance scaling and integration. The vision of the research is to explore a path for technological scale-up that meets the demands for energy efficiency and bandwidth performance for the next decade and beyond.

Intel understands that academia is at the heart of technological innovation and seeks to catalyze research innovation at leading academic institutions around the world. Today’s announcement reflects Intel’s continued commitment to work with universities to develop new and advanced technologies that improve and advance computing as we know it.

Researchers participating in the Research Center include:

  • John bowers, University of California, Santa Barbara

    Project: Heterogeneously integrated quantum dot lasers on silicon.

    The description: The UCSB team will study the problems associated with integrating indium arsenide (InAs) quantum dot lasers with conventional silicon photonics. The objective of this project is to characterize the expected performances and the design parameters of single-frequency and multi-wavelength sources.
  • Pavan Kumar Hanumolu, University of Illinois, Urbana-Champaign

    Project: Low power optical transceivers activated by duobinary signaling and baud rate clock recovery.

    The description: This project will develop ultra-low power, high sensitivity optical receivers using novel trans-impedance amplifiers and baud rate clock and data recovery architectures. Prototypes of optical transceivers will be implemented in a 22nm CMOS process to demonstrate very high jitter tolerance and excellent power efficiency.
  • Arka majumdar, University of Washington

    Project: Reconfigurable non-volatile optical switching network for high bandwidth data communication.

    The description: The UW team will work on low-loss, non-volatile, electrically reconfigurable silicon photonic switches using emerging chalcogenide phase change materials. Unlike existing tunable mechanisms, the developed switch will retain its state, allowing zero static power consumption.
  • Samuel Palermo, Texas A&M University

    Project: Optical transceivers below 150fJ / b for data center interconnects.

    The description: This project will develop high energy efficiency optical transceiver circuits for a massively parallel, high density, high capacity photonic interconnection system. The goal is to improve energy efficiency by using dynamic voltage frequency scaling in transceivers, low oscillation voltage mode drivers, ultra-sensitive optical receivers with tight integration low power photodetectors and optical device tuning loops.
  • Alain wang, Oregon State University

    Project: 0.5V silicon micro-ring modulators driven by high mobility transparent conductive oxide.

    The description: This project aims to develop a low control voltage, high bandwidth silicon micro-ring resonator (MRM) modulator through heterogeneous integration between silicon MOS capacitor with high mobility Ti: In2oh3 The device promises to overcome the energy efficiency bottleneck of the optical transmitter and can be co-packaged in future optical I / O systems.
  • Ming Wu, University of California, Berkeley

    Project: Optical packaging at the scale of a silicon photonics wafer.

    The description: The UC Berkeley team will develop integrated waveguide lenses that have the potential to enable contactless optical conditioning of fiber arrays with low loss and high tolerances.
  • SJ Ben Yoo, University of California, Davis

    Project: Scalable athermal and energy efficient high capacity photonic transceivers.

    The description: The UC Davis team will develop a high energy efficiency athermal photon modulator and resonant photodetector photonic integrated circuits up to 40 Tb / s capacity with 150 fJ / b energy efficiency and I / O density. S of 16 Tb / s / mm. To achieve this, the team will also develop a new 3D packaging technology for the vertical integration of photonic and electronic integrated circuits with an interconnection density of 10,000 pads per square mm.

More context: Intel Labs (press kit)

About Intel

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